1. Field of the Invention
The present invention relates to an insulating gate type field effect transistor (hereinafter referred to as "MOS transistor" but the gate insulating layer thereof is not limited to an oxide layer) and a method of manufacturing the same. More particularly, this invention relates to a MOS transistor of a silicon semiconductor having a silicon gate electrode layer and a method of manufacturing the same.
2. Description of the Related Art
As a metal electrode or a metal interconnection (referred to as "metal electrode" in this specification) in a semiconductor integrated circuit or a single semiconductor element, a metal electrode made of aluminum (Al) has been widely used from a standpoint of workability, electrical conductivity, etc. of the aluminum.
FIG. 1 of the accompanying drawings shows, in cross-sectional form, an example of a conventional MOS transistor of silicon (Si) semiconductor, such as an MOS transistor of a lightly-doped drain type (LDD type) Si semiconductor in which the gate side in the drain thereof is lightly doped. In such an MOS transistor of LDD type Si semiconductor, as shown in FIG. 1, a gate electrode layer 3 made of polycrystalline silicon is formed on a silicon semiconductor portion 1 formed of a silicon semiconductor layer or a silicon semiconductor substrate, for example, through a gate insulating layer 2 made of SiO.sub.2. Then, lightly-doped source and drain portions 4S.sub.1 and 4D.sub.1 are formed by implanting ions or the like, by employing the gate electrode layer 3 and the gate insulating layer 2 as a mask. Thereafter, a side wall 5 of SiO.sub.2 is formed on the side surfaces of the gate electrode layer 3 and the gate insulating layer 2 at their lightly-doped source and drain portion 4S.sub.1 and 4D.sub.1 sides. Heavily-doped source and drain portions 4S.sub.2 and 4D.sub.2 are formed, for example, by implanting ions by using the side wall 5, the gate electrode layer 3 and the gate insulating layer 2 as a mask, thereby a source 4S and a drain 4D being formed, respectively.
Reference numeral 6 depicts an isolating and insulating layer formed on the surface of the silicon semiconductor portion 1 by local oxidation of silicon (LOCOS).
In the aforementioned structure, the upper surface of the resulting structure is covered with an insulating layer 8 of SiO.sub.2. Through electrode windows bored through the insulating layer 8, a source metal electrode 7S, a drain metal electrode 7D and a gate electrode 7G are formed so as to be ohmically connected to the source 4S, the drain 4D and the gate electrode layer 3 of polycrystalline Si, respectively.
When an aluminum layer is used to form the source, drain and gate electrodes 7S, 7D and 7G, there is the problem that the aluminum penetrates into the p-n junctions in the source and drain.
Particularly, since the depth x.sub.j of each of the junctions decreases with the recent advance of scale-reduction of MOS transistor, the aluminum tends to much more penetrate into the junctions. A metal electrode made of aluminum generally employs a multilayer structure in which the Al electrode layer is formed on a separating layer 11, for example, formed by a Ti layer 9 and a TiON layer 10, for separating the aluminum from the silicon.
In the case that such a separating layer is provided, however, the resistance of the contact portions of the electrodes is increased if the thickness of the separating layer is increased so as to positively avoid the penetration of the aluminum.